OBDD Extraction from VHDL Gate Level Descriptions at Design Elaboration

This paper deals with a declarative interface for VHDL in general and the use of such an interface for OBDD based verification of VHDL gate level designs in particular. It presents a solution that enables OBDD verification without external manipulation of the netlist which is well integrated into the standard VHDL environment. The information required for OBDD based VHDL verification, existing and possible future VHDL uses and some advantages of a general declarative interface are illustrated. First experiments with such an interface revealed the advantages of in-place OBDD extraction and helped identify good candidates for VHDL extensions.